
// Library name: ece3663_examples
// Cell name: ak_inverter
// View name: schematic
subckt ak_inverter VDD VSS in out
    M0 (out in VSS VSS) NMOS_VTG w=90n l=50n as=9.45e-15 ad=9.45e-15 \
        ps=300n pd=300n ld=105n ls=105n m=1
    M1 (out in VDD VDD) PMOS_VTG w=180.0n l=50n as=1.89e-14 ad=1.89e-14 \
        ps=390.0n pd=390.0n ld=105n ls=105n m=1
ends ak_inverter
// End of subcircuit definition.

// Library name: ece3663_examples
// Cell name: hw5
// View name: schematic
I2 (net11 0 buff_out dut_out) ak_inverter
I1 (net11 0 net12 buff_out) ak_inverter
I0 (net11 0 net22 net12) ak_inverter
M1 (out dut_out net11 net11) PMOS_VTG w=load_pmos l=50n as=1.89e-13 \
        ad=1.89e-13 ps=2.01u pd=2.01u ld=105n ls=105n m=1
M0 (out dut_out 0 0) NMOS_VTG w=load_nmos l=50n as=9.45e-14 ad=9.45e-14 \
        ps=1.11u pd=1.11u ld=105n ls=105n m=1
V1 (net22 0) vsource type=pwl wave=[ 0 0 100n 0 100.001n vdd ]
V0 (net11 0) vsource dc=vdd type=dc
C0 (out 0) capacitor c=1p
